The invention relates to a method for operating a bus system, in particular in a microprocessor or a microcontroller. Furthermore, the invention relates to a semiconductor device that is suited to perform the method.
In electric or electronic systems, individual system modules communicate via a transmission medium. The system modules may be different electronic devices arranged in a respective component, for instance, different semiconductor devices arranged in a single component. Furthermore, they may be different device sub-components, in particular different components of a semiconductor device, e.g., a memory and/or computing circuit, e.g., a microcontroller or microprocessor, provided in one single device. The transmission medium may, for instance, be a bus or a switch system.
A bus or switch system may connect a plurality of devices or components that use the bus or switch system jointly.
Conventional bus or switch systems may consist of one or several partial systems, for instance, of a data bus for transmitting the actual payload, and/or a control bus for transmitting control data, and/or an address bus for transmitting address data. The data bus as well as the control bus and address bus may include one or several physical data lines each.
A bus or switch system may thus include several transmission channels for the transmission of data, wherein a transmission channel can only be used by one of the connected devices at a time.
In the following, such a transmission channel, via which, for instance, payload or control data or address data can be transmitted and which only one connected device can access at a time, will be referred to as a bus. A system that permits the simultaneous, i.e. temporally parallel transmission of similar data via corresponding transmission channels will be referred to as a switch.
A switch system may thus be formed by a plurality of parallel busses.
If a plurality of system modules are connected with each other via a bus, they act either as a master or as a slave. A master is a system module that is adapted to start a communication on a bus and to actively access the bus to this end. A slave receives such communication or responds to it, is, however, not adapted to start it independently—without being requested. If, for instance, a processor and a memory are connected with each other via a bus, the processor requests, when making a read access to the memory, the memory to provide data. The memory accepts this request and performs the read access and provides the desired data. The processor acts as a master starting the read access, and the memory acts as a slave accepting and performing the read access.
In data processing or control systems, in particular in computer as well as in microprocessor and microcontroller systems, several system modules may be connected with each other via a bus, wherein more than one system module acts as a master. If several masters simultaneously access the bus in an uncoordinated manner to communicate with one or several slaves, they interfere with each other.
Thus, there is the need to coordinate the accesses of the masters such that mutual interferences of the masters are prevented by only one master accessing the bus at a time.
The accesses to a bus are coordinated by an arbiter that is connected with every system module acting as a master and is adapted to exchange data therewith.
In accordance with a conventional method, the arbiter may grant the access permission, for instance, in turns, i.e. pursuant to a round-robin method, to the masters, so that all masters are successively given the possibility of accessing the bus, even if no necessity of access exists for them.
In accordance with a further conventional method, the arbiter may use different information for determining the order of access to the bus. For evaluation of the information, the arbiter includes the logic required for determining the order or access.
Before a master is capable of accessing the bus, this master has to communicate the desired access to the arbiter. In the case of competing accesses to the bus, the arbiter determines the order of accesses and informs a master when it is permitted to access the bus for performing the desired action.
In accordance with a further conventional method, priorities may be assigned to the masters, so that, in the case of simultaneous and thus competing accesses it is always the master with the higher priority that is permitted to access the bus.
In complex bus or switch systems, these methods do, however, not enable an optimum order for competing accesses to a bus, so that they can be performed as quickly as possible and the bus or switch system is utilized as optimally as possible.
One embodiment of the invention provides an improved method for determining the order of access in the case of competing accesses to a bus or switch system.
For these and other reasons, there is a need for the present invention.